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CY62138FV30 MoBL(R)
2-Mbit (256K x 8) Static RAM
Features

Functional Description
The CY62138FV30[1] is a high performance CMOS static RAM organized as 256K words by 8 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery LifeTM (MoBL) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption. Place the device into standby mode reducing power consumption when deselected (CE1 HIGH or CE2 LOW). To write to the device, take Chip Enable (CE1 LOW and CE2 HIGH) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A17). To read from the device, take Chip Enable (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the I/O pins. The eight input and output pins (I/O0 through I/O7) are placed in a high impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or during a write operation (CE1 LOW and CE2 HIGH and WE LOW).
Very High-speed: 45 ns Temperature ranges Industrial: -40 C to 85 C Automotive-A: -40 C to 85 C Wide voltage range: 2.20 V to 3.60 V Pin compatible with CY62138CV25/30/33 Ultra low standby power Typical standby current: 1 A Maximum standby current: 5 A Ultra low active power Typical active current: 1.6 mA at f = 1 MHz Easy memory expansion with CE1, CE2, and OE Features Automatic power down when deselected complementary metal oxide semiconductor (CMOS) for Optimum speed and power Offered in Pb-free 36-Ball VFBGA, 32-Pin TSOP II, 32-Pin SOIC, 32-Pin TSOP I and 32-Pin STSOP Packages

Logic Block Diagram
Note 1. For best practice recommendations, refer to the Cypress application note "System Design Guidelines" at http://www.cypress.com.
Cypress Semiconductor Corporation Document #: 001-08029 Rev. *I
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised November 4, 2010
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Contents
Pin Configuration ............................................................. 3 Product Portfolio .............................................................. 3 Maximum Ratings ............................................................. 4 Electrical Characteristics ................................................ 4 Capacitance ...................................................................... 4 Thermal Resistance.......................................................... 5 Data Retention Characteristics ....................................... 5 Switching Characteristics ................................................ 6 Switching Waveforms ...................................................... 7 Truth Table ........................................................................ 8 Ordering Information........................................................ 9 Ordering Code Definition............................................. 9 Package Diagrams .......................................................... 10 Acronyms ........................................................................ 14 Document Conventions ................................................. 14 Units of Measure ....................................................... 14 Document History Page ................................................. 15 Sales, Solutions, and Legal Information ...................... 16 Worldwide Sales and Design Support ....................... 16 Products .................................................................... 16 PSoC Solutions ......................................................... 16
Document #: 001-08029 Rev. *I
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CY62138FV30 MoBL(R)
Pin Configuration
36-Ball VFBGA (Top View) [2]
1 A0 I/O4 I/O5 VSS VCC I/O6 I/O7 A9 OE A10 NC CE1 A11 A17 A16 A12 A15 A13 2 A1 A2 3 CE2 WE NC 4 A3 A4 A5 5 A6 A7 6 A8 I/O0 I/O1 VCC VSS I/O2 I/O3 A14 A B C D E F G H A17 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
32-Pin SOIC/TSOP II (Top View)
VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3
32-Pin TSOP I (Top View)
32-Pin STSOP (Top View)
A11 A9 A8 A13 WE CE2 A15 VCC A17 A16 A14 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
TSOP I Top View (not to scale)
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3
A11 A9 A8 A13 WE CE2 A15 VCC A17 A16 A14 A12 A7 A6 A5 A4
25 26 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8
STSOP Top View (not to scale)
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3
Product Portfolio
Product Range Min CY62138FV30LL Ind'l/Auto-A 2.2 VCC Range (V) Typ[3] 3.0 Max 3.6 45 Speed (ns) Power Dissipation Operating ICC (mA) f = 1 MHz Typ[3] 1.6 Max 2.5 f = fmax Typ[3] 13 Max 18 Standby ISB2 (A) Typ[3] 1 Max 5
Notes 2. NC pins are not connected on the die. 3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25 C.
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Maximum Ratings
Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature................................. -65 C to +150 C Ambient temperature with power applied ........................................... -55 C to +125 C Supply voltage to ground potential ..........................................................-0.3 V to 3.9 V DC voltage applied to outputs in High-Z State [4, 5] ........................................-0.3 V to 3.9 V
DC input voltage [4, 5] ......................................-0.3 V to 3.9 V Output current into outputs (LOW) .............................. 20 mA Static Discharge Voltage......................................... > 2001 V (MIL-STD-883, Method 3015) Latch-up current ..................................................... > 200 mA Product Range Ambient Temperature VCC [6]
CY62138FV30LL Ind'l/Auto-A -40 C to +85 C 2.2 V to 3.6 V
Electrical Characteristics (Over the Operating Range)
Parameter VOH VOL VIH VIL Description Output HIGH voltage Output LOW voltage Input HIGH voltage Input LOW voltage Test Conditions IOH = -0.1 mA IOH = -1.0 mA, VCC > 2.70 V IOL = 0.1 mA IOL = 2.1 mA, VCC > 2.70 V VCC = 2.2 V to 2.7 V VCC= 2.7 V to 3.6 V VCC = 2.2 V to 2.7 V For BGA package VCC= 2.7 V to 3.6 V VCC = 2.2 V to 3.6 V For other packages IIX IOZ ICC ISB1[8] Input leakage current Output leakage current VCC Operating supply current GND < VI < VCC GND < VO < VCC, output disabled f = fmax = 1/tRC f = 1 MHz Automatic CE Power-down Current CMOS inputs VCC = VCCmax IOUT = 0 mA CMOS levels 1.8 2.2 -0.3 -0.3 -0.3 -1 -1 - - - 45 ns (Ind'l/Auto-A) Min 2.0 2.4 - Typ [7] - - - - - - - - - - - 13 1.6 1 Max - - 0.4 0.4 VCC + 0.3V VCC + 0.3V 0.6 0.8 0.6 +1 +1 18 2.5 5 A Unit V V V V V V V V V A A mA
CE1 > VCC - 0.2 V or CE2 < 0.2 V, VIN > VCC - 0.2 V, VIN < 0.2 V), f = fmax (address and data only), f = 0 (OE, and WE), VCC = 3.60 V
ISB2
[8]
Automatic CE Power-down Current CMOS inputs
CE1 > VCC - 0.2 V or CE2 < 0.2 V, VIN > VCC - 0.2 V or VIN < 0.2 V, f = 0, VCC = 3.60 V
-
1
5
A
Capacitance
Parameter[9] CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = VCC(typ.) Max 10 10 Unit pF pF
Notes 4. VIL(min) = -2.0V for pulse durations less than 20 ns. 5. VIH(max) = VCC+0.75V for pulse durations less than 20 ns. 6. Full device AC operation assumes a 100 s ramp time from 0 to VCC(min) and 200 s wait time after VCC stabilization. 7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25 C 8. Chip enables (CE1 and CE2) must be at CMOS level to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating. 9. Tested initially and after any design or process changes that may affect these parameters.
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Thermal Resistance
Parameter[10] JA JC Description Thermal resistance (Junction to Ambient) Thermal resistance (Junction to Case) Test Conditions Still air, soldered on a 3 x 4.5 inch, two layer printed circuit board SOIC 44.53 24.05 VFBGA 38.49 17.66 TSOP II 44.16 11.97 STSOP 59.72 15.38 TSOP I 50.19 14.59 Unit C/W C/W
Figure 1. AC Test Loads and Waveforms R1 VCC 30 pF INCLUDING JIG AND SCOPE R2 GND Rise Time = 1 V/ns 10%
VCC OUTPUT
ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns
Equivalent to:
THEVENIN EQUIVALENT
OUTPUT
RTH
V
Parameter R1 R2 RTH VTH
2.5 V (2.2 V to 2.7 V) 16667 15385 8000 1.20
3.0 V (2.7 V to 3.6 V) 1103 1554 645 1.75
Unit V
Data Retention Characteristics (Over the Operating Range)
Parameter VDR ICCDR
[12]
Description VCC for data retention Data retention current
Conditions VCC = 1.5 V, CE1 > VCC 0.2 V or CE2 < 0.2 V, VIN > VCC 0.2 V or VIN < 0.2 V Ind'l/Auto-A
Min 1.5 -
Typ[11] - 1
Max - 4
Unit V A
tCDR [10] tR
[13]
Chip deselect to data retention time Operation recovery time Figure 2. Data Retention Waveform [14]
DATA RETENTION MODE VCC
0 45
- -
- -
ns ns
VCC(min)
tCDR
VDR > 1.5V
VCC(min)
tR
CE
Notes 10. Tested initially and after any design or process changes that may affect these parameters. 11. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 2 5C 12. Chip enables (CE1 and CE2) must be at CMOS level to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating 13. Full device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s. 14. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH.
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Switching Characteristics (Over the Operating Range)
Parameter[15] Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write Cycle tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE
[18]
Description
45 ns (Ind'l/Auto-A) Min Max
Unit
Read cycle time Address to data valid Data hold from address change CE1 LOW and CE2 HIGH to data valid OE LOW to data valid OE LOW to Low-Z [16] OE HIGH to High-Z
[16,17] [16]
45 - 10 - - 5 - 10 - 0 -
[16,17]
- 45 - 45 22 - 18 - 18 - 45
ns ns ns ns ns ns ns ns ns ns ns
CE1 LOW and CE2 HIGH to Low Z CE1 HIGH or CE2 LOW to High-Z
CE1 LOW and CE2 HIGH to Power-up CE1 HIGH or CE2 LOW to Power-down Write cycle time CE1 LOW and CE2 HIGH to write end Address setup to write end Address hold from write end Address setup to Write Start WE pulse Width Data setup to write end Data hold from write end WE LOW to High-Z
[16,17]
45 35 35 0 0 35 25 0 - 10
- - - - - - - - 18 -
ns ns ns ns ns ns ns ns ns ns
WE HIGH to Low-Z [16]
Notes 15. Test conditions for all parameters other than tristate parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the AC Test Loads and Waveforms on page 5. 16. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 17. tHZOE, tHZCE, and tHZWE transitions are measured when the output enters a high impedance state. 18. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. Reference the data input setup and hold timing to the edge of the signal that terminates the write.
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Switching Waveforms
Figure 3. Read Cycle 1 (Address transition controlled) [20, 21]
tRC RC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Figure 4. Read Cycle No. 2 (OE controlled) [21, 22, 25]
ADDRESS tRC CE tACE OE tDOE tLZOE HIGH IMPEDANCE DATA OUT VCC SUPPLY CURRENT tPU 50%
[19, 23, 24, 25]
tHZOE tHZCE DATA VALID tPD 50% HIGH IMPEDANCE
tLZCE
ICC ISB
Figure 5. Write Cycle No. 1 (WE controlled)
tWC ADDRESS tSCE CE
tAW tSA WE tPWE
tHA
OE tSD DATA I/O NOTE 26 tHZOE
Notes 19. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. Reference the data input setup and hold timing to the edge of the signal that terminates the write 20. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 21. WE is HIGH for read cycle. 22. Address valid before or similar to CE1 transition LOW and CE2 transition HIGH. 23. Data I/O is high impedance if OE = VIH. 24. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state. 25. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 26. During this period, the I/Os are in output state. Do not apply input signals
tHD
DATA VALID
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Switching Waveforms (continued)
Figure 6. Write Cycle No. 2 (CE1 or CE2 controlled) [27, 28, 29, 30]
tWC ADDRESS tSCE tSA tAW tPWE WE tSD DATA I/O DATA VALID tHD tHA
CE
Figure 7. Write Cycle No. 3 (WE controlled, OE LOW) [27, 30]
tWC ADDRESS tSCE CE
tAW tSA WE tSD DATA I/O NOTE 31 tHZWE DATA VALID tPWE
tHA
tHD
tLZWE
Truth Table
CE1 H X[32] L L L CE2 X[32] L H H H WE X X H H L OE X X L H X High-Z High-Z Data out High-Z Data in Inputs/Outputs Mode Deselect / Power-down Deselect/Power-down Read Output disabled Write Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC)
Notes 27. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 28. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. Reference the data input setup and hold timing to the edge of the signal that terminates the write 29. Data I/O is high impedance if OE = VIH. 30. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains iin high impedance state. 31. During this period, the I/Os are in output state. Do not apply input signals. 32. The `X' (Don't care) state for the Chip enables (CE1 and CE2) in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted.
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CY62138FV30 MoBL(R)
Ordering Information
Speed (ns) 45 Ordering Code CY62138FV30LL-45BVXI CY62138FV30LL-45ZSXI CY62138FV30LL-45ZAXI CY62138FV30LL-45ZXI CY62138FV30LL-45SXI CY62138FV30LL-45ZAXA Package Diagram 51-85149 51-85095 51-85094 51-85056 51-85081 51-85094 Package Type 36-ball VFBGA (Pb-free) 32-pin TSOP II (Pb-free) 32-pin STSOP (Pb-free) 32-pin TSOP I (Pb-free) 32-pin SOIC (Pb-free) 32-pin STSOP (Pb-free) Automotive-A Operating Range Industrial
Ordering Code Definition
CY
621
3
8F
V30
LL
45
XXX
X
Temperature Grades I = Industrial, A = Auto A Package Type BVX: VFBGA (Pb-free) ZSX: TSOP II (Pb-free) ZAX: STSOP (Pb-free) ZX : TSOP I (Pb-free) SX : SOIC (Pb-free) Speed Grade Low Power Voltage Range = 3 V typical Bus Width = x8 F = 90nm Technology Density = 2 Mbit MoBL SRAM Family Coimpany ID: CY = Cypress
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Package Diagrams
Figure 8. 36-Ball VFBGA (6 x 8 x 1 mm), 51-85149
51-85149 *D
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Figure 9. 32-Pin TSOP II, 51-85095
51-85095 *A
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Figure 10. 32-Pin (450 Mil) Molded SOIC, 51-85081
51-85081 *C
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Figure 11. 32-Pin TSOP I (8 x 20 mm), 51-85056
51-85056 * E
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CY62138FV30 MoBL(R)
Figure 12. 32-Pin STSOP (8 x 13.4 mm), 51-85094
51-85094 * E
Acronyms
Acronym CMOS I/O SRAM VFBGA TSOP input/output static random access memory very fine ball grid array thin small outline package Description complementary metal oxide semiconductor
Document Conventions
Units of Measure
Symbol C A mA MHz ns pF V W Unit of Measure degrees Celsius microamperes milliampere megahertz nanoseconds picofarads volts ohms watts
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Document History Page
Document Title: CY62138FV30 MoBL(R), 2-Mbit (256K x 8) Static RAM Document Number: 001-08029 Rev. ** *A *B ECN No. 463660 467351 566724 Submission Date See ECN See ECN See ECN Orig. of Change NXR NXR NXR New data sheet Added 32-pin TSOP II package, 32 pin TSOP I and 32 pin STSOP packages Changed ball A3 from NC to CE2 in 36-ball FBGA pin out Converted from Preliminary to Final Corrected typo in 32 pin TSOP II pin configuration diagram on page #2 (changed pin 24 from CE1to OE and pin 22 from CE to CE1) Changed the ICC(max) value from 2.25 mA to 2.5 mA for test condition f=1 MHz Changed the ISB2(typ) value from 0.5 A to 1 A Changed the ISB2(max) value from 2.5 A to 5 A Changed the ICCDR(typ) value from 0.5 A to 1 A and ICCDR(max) value from 2.5 A to 4 A Added 32-pin SOIC package Updated VIL spec for SOIC, TSOP-II, TSOP-I, and STSOP packages on Electrical characteristics table Corrected typo in the Ordering Information table Added footnote #7 related to ISB2 and ICCDR Updated and converted all tablenotes into Footnote Added Acronyms and Units of Measure table Added Ordering Code Definition Updated All Package Diagrams. Updated datasheet as per new template. Minor changes: Corrected "IO" to "I/O" Corrected 55 C to -55C in Ambient Temperature with Power applied in Maximum Ratings Section Description of Change
*C
797956
See ECN
VKN
*D *E *F *G
809101 940341 2769239 3055119
See ECN See ECN 09/25/09 10/12/2010
VKN VKN RAME
VKN/AESA Included Automotive-A information
*H *I
3061313 3078557
10/15/2010 11/04/2010
RAME RAME
Document #: 001-08029 Rev. *I
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Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturers representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.
Products
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PSoC Solutions
psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5
(c) Cypress Semiconductor Corporation, 2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-08029 Rev. *I
Revised November 4, 2010
Page 16 of 16
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